To enable the users of an integrated circuit to test the functioning of a hybrid board or module incorporating several integrated circuits interconnected among each other in a removable manner, testing systems incorporated in part within the integrated circuits themselves, and capable of cooperating with analogous systems included in the other integrated circuits of the board have been devised.
Standards have been established for that purpose, in particular IEEE Standard 1149.1 which defines the testing means to be incorporated in integrated circuits so that the test of a board may be possible from connection terminals of the board without disassembling the components.
In this Standard each of the integrated circuits incorporates a test circuit comprising in particular:
input/output pins reserved for the test; PA1 an instruction register for storing test instructions entered from the pins reserved for the test; PA1 a logical decoder for the instructions PA1 a shift register with series and parallel inputs, serving mainly to contain test data coming either from the outside (in order to force a desired logical state on certain nodes) or from inside the integrated circuit (in order to observe the state of certain nodes), PA1 a control circuit for the test operations, controlled by pins reserved for the test; the control circuit directly controls the instruction register and indirectly, depending on the instructions of the instruction register, the other registers, the multiplexers and other elements required for the test. PA1 A finite-state machine (i.e. a status register comprising a plurality of cells whose parallel outputs are fed back to the parallel inputs through a logic circuit which is also able to receive external control signals); PA1 Multiplexers associated with the cells of the status register and located between the logic circuit and the cells to enable operation of said status register either serially (i.e., as a shift register) or in parallel; PA1 a control signal generating stage connected at the output of the register to supply control signals of the other elements (in particular registers, multiplexers, locking latches etc.) of the test circuit depending on the state defined by the status register.
FIG. 1 shows an embodiment of the architecture of a test circuit capable of carrying out tests in conformity with the abovementioned Standard. This architecture will be described further on.
The tests that can be carried out with such a circuit are very complex; they comprise generating a great number of test vector sequences which are introduced into the integrated circuit by one of the test pins and in receiving test data vectors from the circuit, also through one of the test pins. The tests are carried out either on the integrated circuit alone (test by the manufacturer, for example) or on the integrated circuit in its environment (test of the circuit on a board and not dissociable from this board).
One of the problems encountered in test procedures is that the test results are reliable only if the internal test circuits themselves are functionally valid. However the test of a circuit takes much time and it is absolutely possible to use up unnecessarily much testing time to find out in the end that the test circuit itself was defective.
In this context it should be remembered that the test procedures constitutes a very important parameter of the manufacturing cost of a complex integrated circuit: each one the circuits must be tested individually and each very thoroughly. The time consumed in tests is considerable in the manufacturing process.
It is obviously difficult to test the testing circuit itself: this test would have to be controlled by another test circuit and other input pins, other control circuits etc. would have to be therefore used.
Additional functional tests of the integrated circuit which would indirectly show up the defects of the test circuit could also be provided. This would however increase the number of test sequences and their length considerably, resulting in considerable costs, especially when many test commands are possible. Verification in each possible case must then be provided for.